1. Field of the Invention
This invention relates to the use of electronic circuits as integrators and more specifically to means for eliminating errors in the output voltage of the integrator due to offset voltages inherent in operational amplifiers used in integrators.
2. Description of the Prior Art
Prior art integrators are well known. The simplest form of integrator utilizing an operational amplifier (shown in FIG. 1) requires a capacitive element 14 with capacitance C to act as a path for negative feedback from the output lead 15 of the operational amplifier 13 to its inverting input lead 9. A resistive element 12 with resistance R is connected in series between the input voltage to be integrated and said inverting input lead 9 of the operational amplifier. The time constant T for such an integrator is simply EQU T=RC. (1)
Switch 25 is connected in parallel across capacitor 14 in order to initialize the integrator by discharging capacitor 14. An ideal operational amplifier 13 will always have inverting input lead 9 at the same potential as noninverting input lead 8, which is connected to ground in the circuit of FIG. 1. An ideal operational amplifier will therefore have its output lead 15 at ground potential as well, when switch 25 is closed. Thus, after initialization has been completed by discharging capacitor 14 through closed switch 25, an ideal operational amplifier connected as shown in FIG. 1 may begin integrating the voltage applied at terminal 11, and the result of the integration will appear on output lead 15 of operational amplifier 13.
Prior art operational amplifiers are well-known. Fabrication tolerances result in component mismatches, thus providing each operational amplifier with its own unique inherent offset voltage V.sub.off. This offset voltage is defined as the output voltage of the operational amplifier when the amplifier is in the unit gain mode (inverting input lead and output lead connected) and its noninverting input lead grounded. Because each operational amplifier has its own unique offset voltage, each circuit utilizing such an operational amplifier must compensate in a unique manner for the inherent offset voltage associated with that specific operational amplifier.
Actual operational amplifiers are imperfect in that the output voltage contains an error component known as the offset voltage (V.sub.OFF). Offset voltages exist due to finite component mismatches within the operational amplifiers. Thus in the circuit of FIG. 1 if operational amplifier 13 is an actual operational amplifier rather than an ideal operational amplifier, the initialized voltage appearing on output lead 15 and inverting input lead 9 of operational amplifier 13 with switch 25 closed will not be zero but will be the offset voltage, V.sub.OFF. This causes the output voltage available on lead 15 to be consistently erroneous by a factor of V.sub.OFF. Because the magnitude of V.sub.OFF is unique for each individual operational amplifier circuit due to unique component mismatches, elimination of the effects of V.sub.OFF is difficult to obtain when manufacturing a large number of circuits. For this reason, operational amplifiers constructed as individual integrated circuits generally have external pins utilized specifically for applying external voltages, as generated by external circuitry, to null the offset voltage of the operational amplifier. However, integrators contained as a subcircuit of an integrated circuit chip do not provide the end user with external access to the operational amplifier unless additional pins on the integrated circuit package are specifically made available for this purpose. In all but the most rare circumstances this is totally impractical. It is also undesirable to require external circuitry to eliminate V.sub.OFF.
In the construction of metal oxide silicon (MOS) semiconductor devices, values of resistors and capacitors are not highly controllable. Thus in the integrator circuit shown in FIG. 1 with the time constant equal to RC, circuits constructed utilizing MOS techniques will possess unpredictable time constants.
In practice, resistors are generally formed by diffusion, resulting in resistance values and resistance ratios which are not highly controllable. Capacitors are formed by utilizing layers of conductive material, such as metal or polycrystalline silicon, as capacitor plates. Each plate of conductive materials is separated by a layer of electrical insulation material, such as SiO.sub.2 or silicon nitride, serving as a dielectric from another conductive layer or from a conductive substrate. While capacitor areas are quite controllable, dielectric thickness is not. However, this is not fatal from a circuit point of view because while capacitance values are not highly controllable, ratios of capacitance values are, since dielectric thickness is quite uniform across a single semiconductor die.
One method of circumventing the problem of uncontrollable RC time constants in MOS devices is to replace each resistor with a switched capacitor, as described by Caves, et al., in "Sampled Analog Filtering Using Switched Capacitors As Resistor Equivalents", IEEE JSSC, Volume SC-12, Number 6, December 1977. One such switched capacitor resistor equivalent is shown in FIG. 2a. Terminals 71 and 75 are available as equivalents to the terminals available on a resistor. Capacitor 74 has a capacitance value of C. Switch 72 is connected in series between input terminal 71 and capcitor 74, and controls when the input voltage is applied to capacitor 74 from terminal 71.
Switch 73 is connected in series between output terminal 75 and capacitor 74, and controls when the voltage stored in capacitor 74 is applied to output terminal 75. In practice, switches 72 and 73 are controlled by two clock generators having the same frequency of operation but generating non-overlapping control pulses. When the clock controlling switch 72 goes high, switch 72 closes, thus causing capacitor 74 to be charged to the input voltage applied to terminal 71. Because the two clock generators are non-overlapping, switch 73 is open during this charge cycle. Switch 72 then opens. Then switch 73 closes, while switch 72 remains open, thus applying the voltage stored on capacitor 74 to terminal 75.
Another switched capacitor resistor equivalent is shown in FIG. 2b. Terminals 171 and 175 are available as equivalents to the terminals available on a resistor. Capacitor 174 has a capacitance value of C. Switch 172 is connected in series between input terminal 171 and capacitor 174, and controls when the input voltage is applied to capacitor 174 from terminal 171.
Switch 173 is connected between capacitor 174 and ground, and controls when the charge stored in capacitor 174 is removed. In practice, switches 172 and 173 are controlled by two clock generators having the same frequency of operation but generating non-overlapping control pulses. When the clock controlling switch 172 goes high, switch 172 closes, thus causing capacitor 174 to accept charge from the input voltage applied to terminal 171. Because the two clock generators are non-overlapping, switch 173 is open during this charge cycle. Switch 172 then opens. Then switch 173 closes, while the switch 172 remains open, thus discharging capacitor 174 to ground.
The resistor equivalent circuits of FIGS. 2a and 2b simulates a resistor having resistance value R given by the following equation: EQU R=t/C.sub.R ( 2)
where t is the period of switches 72 and 73, (FIG. 2a) and 172-173 (FIG. 2b) in seconds, and C.sub.R is the capacitance of resistor equivalent capacitor 74 (FIG. 2a) and capacitor 174 (FIG. 2b). From equations 1 and 2 we can see that the time constant for the integrator of FIG. 1 utilizing a switched capacitor as a resistor equivalent will be EQU T=(tC/C.sub.R) (3)
or that the bandwidth will be EQU BW=fC.sub.R /C (4)
where C is the capacitance of the integrating capacitor 14 and f is the frequency of operation of switch 72 and switch 73 and is equal to 1/t. Since the time constant of an integrator utilizing a switched capacitor as a resistor equivalent is dependent on the ratio of capacitors, it is possible to construct many devices having a uniform capacitance ratio and thus uniform time constants.
A circuit equivalent to the integrator shown in FIG. 1 utilizing switched capacitor resistor equivalents is shown in FIG. 3 of co-pending U.S. patent application Ser. No. 185,356. Of importance, the circuit of FIG. 3 of the co-pending application shows two switches (switch 24 and switch 25) connected to inverting input lead 40 of operational amplifier 48. The connection of a switch to the inverting input lead of an operational amplifier decreases the accuracy of the integrator due to leakage currents caused by each such switch.
Thus, integrators fabricated utilizing MOS techniques have been constructed utilizing switched capacitors in place of resistive elements. Switched capacitor integrators constitute an improvement over integrators utilizing resistive elements due to the fact that resistance values of diffused resistors are not easily controllable in MOS circuits while the ratios of capacitance values are more controllable. However, switched capacitor resistive equivalents have no effect on the inherent offset of the operational amplifiers used in switched capacitor MOS integrators. Thus, output voltage error due to voltage offsets of operational amplifiers are present both in integrators utilizing resistive and capacitive elements and in integrators utilizing switched capacitor elements in place of said resistive elements.
To improve accuracy it is desirable to reduce or eliminate the voltage offsets associated with the output signal of an operational amplifier. One method and structure for eliminating the effect of voltage offsets on the output signal of a switched capacitor integrator is disclosed in co-pending U.S. patent application Ser. No. 185,356 filed Sept. 8, 1980 now U.S. Pat. No. 4,365,204 and assigned to American Microsystems, Inc., the assignee of this invention. U.S. Pat. No. 4,365,204 is hereby incorporated by reference into this application.